Hardware and Software Co-design Issues in H.264 Decoder

In this paper we talk about mixed architectures of a H.264/AVC video decoder. Here software part of decoder was implemented in NIOS II processor on a FPGA prototyping board (Stratix III). Software and hardware architectures was proposed to increase the decoder output performance. Based upon the time execution parameters, data dependency constraints, the decoder partitioning is applied. Here the inverse 4x4 Intra process is implemented with hardware accelerator. It consists of inverse 4x4 Intra prediction, inverse transformation and inverse quantization. By implementing inter prediction as a hardware module the decoder through can be increased